Hybrid full-hardware implementation of NIST Post-Quantum Cryptography KEM and Digital Signature H/F

Description du poste:

Position description

Category

Electronics components and equipments

Contract

Internship

Job title

Hybrid full-hardware implementation of NIST Post-Quantum Cryptography KEM and Digital Signature H/F

Subject

The National Institute for Standard and Technology (NIST) has recently emitted (on August 2024) the new standards for Key Encapsulation Mechanism (KEM) and digital signature based on lattice-based cryptography (CRYSTALS-Kyber and CRYSTALS-Dilithium) and hash-based cryptography (SPHINCS+). The proposed internship will focus on the full-hardware implementation of the NIST's newly standardized post-quantum cryptographic algorithms. The primary objective is to design and optimize hybrid hardware architectures that efficiently support multiple cryptographic schemes while minimizing resource usage. By mutualizing key hardware components, such as arithmetic units and memory blocks, the project aims to achieve a flexible and scalable solution for FPGA and ASIC platforms.

Contract duration (months)

6

Job description

Internship description
The National Institute for Standard and Technology (NIST) has recently emitted (on August 2024) the new standards for Key Encapsulation Mechanism (KEM) and digital signature based on lattice-based cryptography (CRYSTALS-Kyber and CRYSTALS-Dilithium) and hash-based cryptography (SPHINCS+). The proposed internship will focus on the full-hardware implementation of the NIST's newly standardized post-quantum cryptographic algorithms. The primary objective is to design and optimize hybrid hardware architectures that efficiently support multiple cryptographic schemes while minimizing resource usage. By mutualizing key hardware components, such as arithmetic units and memory blocks, the project aims to achieve a flexible and scalable solution for FPGA and ASIC platforms.
Desired skills and experience
This offer is dedicated to master students looking for an ambitious research-oriented internship. If you are looking for an experience in ASIC design with industrial-grade tools and processes, this internship is perfect for you! It is required to have graduate-level experience in ASIC-oriented design and be familiar with arithmetic circuit microarchitectures, RTL modelling (VHDL or Verilog/SystemVerilog) and synthesis (Synopsys Design Compiler).
Conditions
This internship is intended for master (or engineering school) students in their last year. It is possible to base the master's thesis on the subjects treated during the internship. A funded PhD position will be opened at the end of the internship. The student will have a 6-month remunerated stage contract, plus benefits for accommodation in Grenoble and public transportation.

Applicant Profile

Conformément aux engagements pris par le CEA en faveur de l'intégration de personnes en situation de handicap, cet emploi est ouvert à tous et toutes.

Position location

Site

Grenoble

Job location

France, Auvergne-Rhône-Alpes, Isère (38)

Location

Grenoble

Candidate criteria

PhD opportunity

Oui

Requester

Position start date

01/01/2025