Master Thesis: Local Clock Gating Optimization for EMCA Accelerator IP Arrays

Description du poste:

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About this opportunity:
(COMPANY NAME)'s many-core architecture, EMCA, is a purpose-built architecture for radio signal processing with arrays of task-specific cores, i.e. HW accelerators (HWA), with local storage to handle the extreme data rates and the multi-dimensional nature of the processing. Energy performance is imperative for the EMCA accelerators IP portfolio for energy consumption and heat dissipation reasons, which if not optimal can in turn drive operating expenses, cost, and physical dimensions upwards for a SoC ASIC product. The development of requirements on such HWA IP blocks in terms of energy performance, as well as capacity, clearly outpaces Moore's law, thus calling for a higher focus on frontend microarchitectural optimizations for low power across all operating points.

HWA IP arrays typically employ hierarchical clock gating mechanisms to ensure coarse-grained power savings, thus satisfying the basic energy efficiency requirements for the idling operating point. However, for other operating points where the hierarchical clock gating is not applicable, these blocks must rely on an optimal local clock gating efficiency and eliminate any redundant switching activity to meet the set requirements for energy performance based on real-time actual processing need. Prior analyses indicate that there are remaining power optimization opportunities for registers, memories, combinational logic, and the lower levels of the clock tree. The scope of this thesis is to profile the key EMCA HWA IP blocks, and across their full operating points spectrum identify and deliver on such optimization opportunities. This by exploring and employing a hybrid flow that features automatic power optimization with integrated formal verification guarantees for bug-free RTL for the "low hanging fruits", together with a manual optimization flow for the more advanced changes including synthesis "clock gating knobs" optimization.

What you will do:

The assignment of this thesis is twofold. The first goal is to pipeclean and employ the hybrid analysis and optimization flow for the key blocks in the HWA IP portfolio, to characterize the blocks across different operating points.

▪ Identify the optimal time windows and testcases for power profiling and optimization.

o Once the maximum, typical, low and idle operating points are established, create a curve for metrics across all operating points by interpolation to capture the baseline of energy efficiency.

▪ Devise a modular approach to power optimization exploration by dividing the IP into subblocks, then exercise each subblock independently to identify optimization opportunities starting with boundary conditions and important testcases first.
The second goal is the subsequent targeted optimization for each HWA IP RTL model, using the hybrid flow.

▪ A first pass of RTL code optimization, to boost the local clock gating efficiency, using formally-verified automatic RTL generation.

▪ Iterative manual updates, based on differential energy analysis, to remove residual power bugs to meet and exceed the power metrics. Capture the improved energy efficiency metrics curves.

The skills you bring:

This project aims at students in electrical/computer engineering, computer science or similar. Background in ASIC design, RTL HDL coding, basic testbench design using SystemVerilog, and scripting (Tcl/Python) for EDA tools is preferred.

​What happens once you apply?
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Primary country and city: Sweden (SE) || Stockholm
Job Stage: Job Stage 4
Primary Recruiter: Arvid Bergström